公开(公告)号：US12300621B2

公开(公告)日：2025-05-13

申请号：US17583895

申请日：2022-01-25

Applicant: Infinera Corp.

Inventor： John W. Osenbach ,  Jiaming Zhang

IPC: H01L23/538 ,  H01L23/64 ,  H01L49/02

Abstract: Disclosed herein are multi-layer substrates for integrated circuit packages and methods of making the same. The multi-layer substrate may comprise a plurality of lower layers, at least one core layer, a plurality of upper layers, and a side surface. A first connection and a second connection may extend through or on an uppermost layer of the plurality of upper layers. A trace may be embedded in or on one of the plurality of upper layers, the trace electrically connected to the first connection and the second connection. A first mounting pad and a second mounting pad may be positioned on the side surface and/or the uppermost layer of the plurality of upper layers and a blocking capacitor may be electrically connected to the first mounting pad and the second mounting pad with the second mounting pad electrically connected to the second connection.

公开(公告)号：US12218031B2

公开(公告)日：2025-02-04

申请号：US17568535

申请日：2022-01-04

Applicant: Infinera Corp.

Inventor： John W. Osenbach ,  Gannon Reichert ,  Vinh Nguyen

IPC: H01L23/433 ,  H01L21/50 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: Systems and methods of providing a bare circuit integrated circuit package with a containment ring are described. The bare circuit integrated circuit package may be provided with a substrate connected to a printed circuit board. An integrated circuit may be connected to the substrate. A stiffener ring that surrounds the integrated circuit may be attached to the substrate. A heat sink may be positioned on the stiffener ring and over the integrated circuit such that there is a space between a top of the integrated circuit and a bottom surface of the heat sink. A thermal interface material may be provided to thermally connect the integrated circuit and the heat sink. A containment ring may be positioned between the stiffener ring and the integrated circuit, the containment ring sized and positioned to prevent pumping and/or displacement of the thermal interface material.

公开(公告)号：US20220216127A1

公开(公告)日：2022-07-07

申请号：US17568535

申请日：2022-01-04

Applicant: Infinera Corp.

Inventor： John W. Osenbach ,  Gannon Reichert ,  Vinh Nguyen

IPC: H01L23/433 ,  H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L21/50

Abstract: Systems and methods of providing a bare circuit integrated circuit package with a containment ring are described. The bare circuit integrated circuit package may be provided with a substrate connected to a printed circuit board. An integrated circuit may be connected to the substrate. A stiffener ring that surrounds the integrated circuit may be attached to the substrate. A heat sink may be positioned on the stiffener ring and over the integrated circuit such that there is a space between a top of the integrated circuit and a bottom surface of the heat sink. A thermal interface material may be provided to thermally connect the integrated circuit and the heat sink. A containment ring may be positioned between the stiffener ring and the integrated circuit, the containment ring sized and positioned to prevent pumping and/or displacement of the thermal interface material.

公开(公告)号：US20220238449A1

公开(公告)日：2022-07-28

申请号：US17583895

申请日：2022-01-25

Applicant: Infinera Corp.

Inventor： John W. Osenbach ,  Jiaming Zhang

IPC: H01L23/538 ,  H01L23/64 ,  H01L49/02

Abstract: Disclosed herein are multi-layer substrates for integrated circuit packages and methods of making the same. The multi-layer substrate may comprise a plurality of lower layers, at least one core layer, a plurality of upper layers, and a side surface. A first connection and a second connection may extend through or on an uppermost layer of the plurality of upper layers. A trace may be embedded in or on one of the plurality of upper layers, the trace electrically connected to the first connection and the second connection. A first mounting pad and a second mounting pad may be positioned on the side surface and/or the uppermost layer of the plurality of upper layers and a blocking capacitor may be electrically connected to the first mounting pad and the second mounting pad with the second mounting pad electrically connected to the second connection.