公开(公告)号：US20030188271A1

公开(公告)日：2003-10-02

申请号：US10261235

申请日：2002-09-30

Applicant: Institute of High Performance Computing

Inventor： Wenjun Zhuang ,  Olivier Laurent Peyran ,  Zheng Zeng ,  Ping Bai

IPC: G06F017/50

CPC classification number: G06F17/5045

Abstract: The invention relates to an IC chip-planning system and method to provide automatic creation and optimisation of chip-level design plan alternatives that can meet user-specific target chip area/design density, chip shape/aspect ratio, delay/timing closure, and/or congestion/routability objectives at each level of the designnullarchitectural, RTL, gate, structural and physical levels. By combining global searching and local searching, a multi-objective optimisation process and a single-objective optimisation process, the invention can greatly reduce searching and optimisation time. Flexible system structure allows for generation of the optimised chip-planning solutions via an open optimisation train, a small optimisation loop, and/or a large optimisation loop. With a function module to extract the topological relationship between blocks or gene structure from existing solutions whether from previous designs or manual designs, the invention may also successfully combine human experience and/or work with other EDA tools. A parallel system structure with redundancy elimination is preferably employed to attain high performance in the chip-planning. The invention has the potential to produce near optimal chip-planning solutions to meet the requirements for system-on-chip IC designs having more than 100 million gates and 1 GHz frequency.

Abstract translation: 本发明涉及一种IC芯片规划系统和方法，用于提供能够满足用户特定的目标芯片面积/设计密度，芯片形状/宽高比，延迟/时序闭合的芯片级设计方案的自动创建和优化。 /或设计架构，RTL，门，结构和物理层面的每个级别的拥塞/可路由目标。 通过组合全局搜索和局部搜索，多目标优化过程和单目标优化过程，本发明可以大大减少搜索和优化时间。 灵活的系统结构允许通过开放优化列车，小型优化循环和/或大型优化循环来生成优化的芯片规划解决方案。 利用功能模块从现有解决方案中提取块或基因结构之间的拓扑关系，无论是从先前的设计还是手工设计，本发明还可以将人类经验和/或工作与其他EDA工具相结合。 优选采用具有冗余消除的并行系统结构以在芯片规划中获得高性能。 本发明具有生产接近最佳芯片规划解决方案的潜力，以满足具有超过1亿门和1GHz频率的片上集成电路设计的要求。