公开(公告)号：US20250112140A1

公开(公告)日：2025-04-03

申请号：US18374609

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rahul BHURE ,  Mitchell PAGE ,  Joseph PEOPLES ,  Jieying KONG ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Bainye Francoise ANGOUA ,  Yosef KORNBLUTH ,  Daniel ROSALES-YEOMANS ,  Joshua STACEY ,  Aaditya Anand CANDADAI ,  Yonggang Yong LI ,  Tchefor NDUKUM ,  Scott COATNEY ,  Gang DUAN ,  Jesse JONES ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Dilan SENEVIRATNE ,  Matthew ANDERSON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.

公开(公告)号：US20240203664A1

公开(公告)日：2024-06-20

申请号：US18081362

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Yosef KORNBLUTH ,  Bainye Francoise ANGOUA ,  Whitney BRYKS ,  Daniel ROSALES-YEOMANS ,  Aaditya Anand CANDADAI ,  Holly CLINGAN ,  Jade Sharee LEWIS ,  Patrick QUACH ,  Srinivas V. PIETAMBARAM

IPC: H01G4/33 ,  H01G4/10

CPC classification number: H01G4/33 ,  H01G4/105

Abstract: Embodiments disclosed herein include a core for a package substrate. In an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. In an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.

公开(公告)号：US20240177907A1

公开(公告)日：2024-05-30

申请号：US18059992

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Yosef KORNBLUTH ,  Whitney BRYKS ,  Ravindranadh ELURI ,  Aaditya Anand CANDADAI ,  Srinivas PIETAMBARAM

IPC: H01F7/20 ,  B32B3/18

CPC classification number: H01F7/206 ,  B32B3/18 ,  B32B15/18

Abstract: The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.

公开(公告)号：US20240153857A1

公开(公告)日：2024-05-09

申请号：US17983230

申请日：2022-11-08

Applicant: Intel Corporation

Inventor： Bainye Francoise ANGOUA ,  Whitney BRYKS ,  Yosef KORNBLUTH ,  Daniel ROSALES-YEOMANS ,  Holly CLINGAN ,  Patrick QUACH ,  Jade Sharee LEWIS ,  Aaditya Anand CANDADAI

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16225

Abstract: Embodiments disclose a package substrate. In an embodiment, the package substrate comprises a core, where the core comprises: a first sub-core, where the first sub-core comprises a glass and a first through glass via (TGV), and a second sub-core, where the second sub-core comprises the glass and a second TGV. In an embodiment, the first TGV directly contacts the second TGV.

公开(公告)号：US20240186197A1

公开(公告)日：2024-06-06

申请号：US18060592

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaditya Anand CANDADAI ,  Nicholas HAEHN ,  Ao WANG ,  Whitney BRYKS ,  Srinivas PIETAMBARAM

IPC: H01L23/16

CPC classification number: H01L23/16

Abstract: The present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. In an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. In yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated structures.