公开(公告)号：US20220308995A1

公开(公告)日：2022-09-29

申请号：US17214835

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Adrian C. MOGA ,  Abhishek SHARMA

IPC: G06F12/0802

Abstract: Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.

公开(公告)号：US20180225213A1

公开(公告)日：2018-08-09

申请号：US15947831

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David BUBIEN ,  Eric DELANO

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20180225211A1

公开(公告)日：2018-08-09

申请号：US15947829

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David Bubien ,  Eric Delano

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20180225212A1

公开(公告)日：2018-08-09

申请号：US15947830

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David BUBIEN ,  Eric DELANO

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.