公开(公告)号：US10318427B2

公开(公告)日：2019-06-11

申请号：US14575525

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Ramon Matas ,  Chung-Lun Chan ,  Alexey P. Suprun ,  Aditya Kesiraju

IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/0886 ,  G06F9/38

Abstract: An instruction in a first cache line may be identified and an address associated with the instruction may be determined. The address may be determined to cross a cache line boundary associated with the first cache line and a second cache line. In response to determining that the address crosses the cache line boundary, the instruction may be adjusted based on a portion of the address included in the first cache line and a second instruction may be created based on a portion of the address included in the second cache line. The second instruction may be injected into an instruction pipeline after the adjusted instruction.

公开(公告)号：US10175986B2

公开(公告)日：2019-01-08

申请号：US15589510

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Roger Gramunt ,  Ramon Matas ,  Benjamin C. Chaffin ,  Neal S. Moyer ,  Rammohan Padmanabhan ,  Alexey P. Suprun ,  Matthew G. Smith

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

公开(公告)号：US20170242698A1

公开(公告)日：2017-08-24

申请号：US15589510

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Roger Gramunt ,  Ramon Matas ,  Benjamin C. Chaffin ,  Neal S. Moyer ,  Rammohan Padmanabhan ,  Alexey P. Suprun ,  Matthew G. Smith

IPC: G06F9/30 ,  G06F11/30 ,  G06F11/34 ,  G06F9/38 ,  G06F11/36

CPC classification number: G06F9/3016 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3855 ,  G06F9/3857 ,  G06F11/3024 ,  G06F11/34 ,  G06F11/3466 ,  G06F11/36 ,  G06F11/362 ,  G06F11/3636

Abstract: A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

公开(公告)号：US09886396B2

公开(公告)日：2018-02-06

申请号：US14581285

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Roger Gramunt ,  Rammohan Padmanabhan ,  Ramon Matas ,  Neal S. Moyer ,  Benjamin C. Chaffin ,  Avinash Sodani ,  Alexey P. Suprun ,  Vikram S. Sundaram ,  Chung-Lun Chan ,  Gerardo A. Fernandez ,  Julio Gago ,  Michael S. Yang ,  Aditya Kesiraju

IPC: G06F9/30 ,  G06F9/44 ,  G06F12/12 ,  G06F12/122 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F12/122 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/4806 ,  G06F2212/62

Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.