公开(公告)号：US20230315473A1

公开(公告)日：2023-10-05

申请号：US17712139

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Muhammad Azeem ,  Rangeen Basu Roy Chowdhury ,  Xiang Zou ,  Malihe Ahmadi ,  Joju Joseph Zajo ,  Ariel Sabba ,  Ammon Christiansen ,  Polychronis Xekalakis ,  Eliyah Kilada

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/382 ,  G06F9/3873 ,  G06F9/30149

Abstract: Embodiments of apparatuses and methods for variable-length instruction steering to instruction decode clusters are disclosed. In an embodiment, an apparatus includes a decode cluster and chunk steering circuitry. The decode cluster includes multiple instruction decoders. The chunk steering circuitry is to break a sequence of instruction bytes into a plurality of chunks, create a slice from a one or more of the plurality of chunks based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks, wherein the slice has a variable size and includes a plurality of instructions, and steer the slice to the decode cluster.

公开(公告)号：US20200310801A1

公开(公告)日：2020-10-01

申请号：US16367171

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Srikanth Srinivasan ,  Matthew Merten ,  Ammon Christiansen

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/22

Abstract: A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.

公开(公告)号：US10956160B2

公开(公告)日：2021-03-23

申请号：US16367171

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Srikanth Srinivasan ,  Matthew Merten ,  Ammon Christiansen

IPC: G06F9/30 ,  G06F9/22 ,  G06F9/38 ,  G06F9/48

Abstract: A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.

公开(公告)号：US11126438B2

公开(公告)日：2021-09-21

申请号：US16452955

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Thomas Mullins ,  Ammon Christiansen ,  James Hadley ,  Robert S. Chappell ,  Sean Mirkes

IPC: G06F9/22 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a reservation station of a processor includes: a plurality of first lanes having a plurality of entries to store information for instructions having in-order dependencies; a variable latency tracking table including a second plurality of entries to store information for instructions having a variable latency; and a scheduler circuit to access a head entry of the plurality of first lanes to schedule, for execution on at least one execution unit, at least one instruction from the head entry of at least one of the plurality of first lanes. Other embodiments are described and claimed.