公开(公告)号：US20220334963A1

公开(公告)日：2022-10-20

申请号：US17849387

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Ankit PATEL ,  Lidia WARNES ,  Donald L. FAW ,  Bassam N. COURY ,  Douglas CARRIGAN ,  Hugh WILKINSON ,  Ananthan AYYASAMY ,  Michael F. FALLON

IPC: G06F12/06 ,  G06F12/0877 ,  G06F12/0868

Abstract: Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.

公开(公告)号：US20250156356A1

公开(公告)日：2025-05-15

申请号：US18834582

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Somnath PAUL ,  Muhammad M. KHELLAH ,  Nilesh JAIN ,  Gopi Krishna JHA ,  Ravishankar IYER ,  Theodore WILLKE ,  Mariano TEPPER ,  Maria Cecilia AGUERREBERE OTEGUI ,  Nagabhushan CHITLUR ,  Suresh THIRUMANDAS ,  Ananthan AYYASAMY ,  Sujoy SEN ,  Xiao HU

IPC: G06F13/40 ,  G06F13/16

Abstract: Examples include techniques to utilize near memory compute circuitry for memory-bound workloads. Examples include the near memory compute circuitry being resident on an input/output (I/O) arranged to couple with a plurality of memory devices configured as a memory pool that is accessible to a host central processing unit (CPU) through the I/O switch. The near memory compute circuitry may receive a request to obtain data from the memory pool and generate a result that is made available to the host CPU to facilitate acceleration of a memory-bound workload.