公开(公告)号：US20210193196A1

公开(公告)日：2021-06-24

申请号：US16725747

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Turbo Majumder ,  Iqbal Rajwani ,  Andrew Lines ,  Altug Koker ,  Lakshminarayanan Striramassarma ,  Muhammad Khellah

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

公开(公告)号：US11908542B2

公开(公告)日：2024-02-20

申请号：US16725747

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Turbo Majumder ,  Iqbal Rajwani ,  Andrew Lines ,  Altug Koker ,  Lakshminarayanan Striramassarma ,  Muhammad Khellah

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.