公开(公告)号：US20200006302A1

公开(公告)日：2020-01-02

申请号：US16022677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/64

Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.

公开(公告)号：US20230299044A1

公开(公告)日：2023-09-21

申请号：US17698928

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Arghya Sain ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3025 ,  H01L2225/06537 ,  H01L2225/06586

Abstract: In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.

公开(公告)号：US20180270948A1

公开(公告)日：2018-09-20

申请号：US15675883

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H05K1/02 ,  H02H9/04 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US10015878B2

公开(公告)日：2018-07-03

申请号：US14945762

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H9/04 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US11569173B2

公开(公告)日：2023-01-31

申请号：US15857752

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Digvijay A. Raorane ,  Wilfred Gomes ,  Ravindranath V. Mahajan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/50 ,  H01L25/18

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

公开(公告)号：US11462521B2

公开(公告)日：2022-10-04

申请号：US16022677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/64 ,  H01L23/36

Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.

公开(公告)号：US20160309580A1

公开(公告)日：2016-10-20

申请号：US14945762

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US09225164B2

公开(公告)日：2015-12-29

申请号：US14534979

申请日：2014-11-06

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H3/22 ,  H02H9/04 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract translation: 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。