LOW-LATENCY OPTICAL CONNECTION FOR CXL FOR A SERVER CPU

    公开(公告)号:US20220114125A1

    公开(公告)日:2022-04-14

    申请号:US17067365

    申请日:2020-10-09

    Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

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