公开(公告)号：US09678750B2

公开(公告)日：2017-06-13

申请号：US13795234

申请日：2013-03-12

Applicant: Intel Corporation

Inventor： Mikhail Smelyanskiy ,  Victor Lee ,  Christopher Hughes ,  Daehyun Kim ,  Yen-Kuang Chen ,  Changkyu Kim ,  Jatin Chhugani ,  Anthony D. Nguyen ,  Sanjeev Kumar

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06T5/40 ,  H04N1/407 ,  G06K9/62

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3885 ,  G06K9/6212 ,  G06T5/40 ,  H04N1/4074

Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.