公开(公告)号：US20220196937A1

公开(公告)日：2022-06-23

申请号：US17132851

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bassam ZIADEH ,  Jingyi HUANG ,  Yiqun BAI ,  Ziyin LIN ,  Vipul MEHTA ,  Joseph VAN NAUSDLE

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

公开(公告)号：US20250062168A1

公开(公告)日：2025-02-20

申请号：US18451852

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Justin WHETTEN ,  Zhou YANG ,  Zheng KANG ,  Haowen LIU ,  Bassam ZIADEH ,  Vijay Krishnan SUBRAMANIAN ,  John HARPER ,  Pramod MALATKAR ,  Patrick NARDI ,  Anthony MONTERROSA ,  Michael TAN ,  Sean BUSHELL

IPC: H01L23/24 ,  B23K26/362 ,  H01L21/268 ,  H01L21/67

Abstract: The present disclosure is directed to a patterned stiffener that includes a metallic body, which is a component of and is attached to a semiconductor device platform for providing rigidity. In an aspect, there are patterned sections formed on the metallic body that act to modulate the metallic body to obtain a desired configuration for the semiconductor device platform. In another aspect, the present disclosure is also directed to a method that includes providing a platform for forming an electronic component, disposing a stiffener having a metallic body on the platform, disposing at least one semiconductor device onto the platform, performing one or more bonding process steps, and exposing the stiffener to localized heating to modulate changes in the stiffener to a pre-determined shape or desired configuration.

公开(公告)号：US20240402445A1

公开(公告)日：2024-12-05

申请号：US18798574

申请日：2024-08-08

Applicant: Intel Corporation

Inventor： Bassam ZIADEH ,  Jingyi HUANG ,  Yiqun BAI ,  Ziyin LIN ,  Vipul MEHTA ,  Joseph VAN NAUSDLE

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

公开(公告)号：US20230290661A1

公开(公告)日：2023-09-14

申请号：US17692247

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Kirk WHEELER ,  Emily SCHUBERT ,  Dingying XU ,  Bassam ZIADEH

IPC: H01L21/673

CPC classification number: H01L21/67336 ,  H01L21/67356 ,  H01L21/67366 ,  H01L21/67369 ,  H01L21/67386 ,  H01L21/67396

Abstract: The present disclosure relates to a tray assembly. The tray assembly may include a die transport tray. The die transport tray may include an inner bottom surface for accommodating a plurality of dies. The tray assembly may further include a lid. The lid may include an inner top surface, wherein the inner top surface of the lid may face the inner bottom surface of the die transport tray when the lid is assembled over the die transport tray. The lid may further include a shock absorbing material on the inner top surface for contacting the plurality of dies, if present.

公开(公告)号：US20210233867A1

公开(公告)日：2021-07-29

申请号：US16752457

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Bassam ZIADEH ,  Joseph VAN NAUSDLE ,  Zhou YANG ,  William J. LAMBERT ,  Mitul MODI

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L21/50

Abstract: Embodiments herein describe techniques for an IC package including a supporting layer having a first zone and a second zone. An electronic component is placed above the first zone of the supporting layer. An underfill material is formed above the first zone of the supporting layer, around or below the electronic component to support the electronic component. The second zone of the supporting layer includes a base area and multiple micro-pillars above the base area, where any two micro-pillars of the multiple micro-pillars are separated by a gap in between. The second zone has a hydrophobic surface including surfaces of the multiple micro-pillars and surfaces of the base area. The second zone is a keep out zone to prevent the underfill material from entering the second zone. Other embodiments may be described and/or claimed.