公开(公告)号：US20220407226A1

公开(公告)日：2022-12-22

申请号：US17352394

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Benjamin JANN ,  Ashoke RAVI

IPC: H01Q3/38 ,  H03H17/02 ,  H03M1/66 ,  H01Q3/26 ,  H04L7/08 ,  H04B7/08

Abstract: A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.

公开(公告)号：US20220416770A1

公开(公告)日：2022-12-29

申请号：US17356564

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ali AZAM ,  Ashoke RAVI ,  Benjamin JANN

IPC: H03K5/00 ,  G06F7/68 ,  H03K5/02

Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

公开(公告)号：US20240214248A1

公开(公告)日：2024-06-27

申请号：US18145874

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Wayne BALLANTYNE ,  Kannan RAJAMANI ,  Benjamin JANN ,  Zoran ZIVKOVIC ,  Kameran AZADET

IPC: H04L25/03

CPC classification number: H04L25/03949 ,  H04L25/0391 ,  H04L25/03961

Abstract: An apparatus for controlling an equalizer is provided. The apparatus comprises interface circuitry configured to receive at least one of an input signal and an output signal of the equalizer. The apparatus further comprises processing circuitry configured to determine at least one signal metric based on the at least one of the input signal and the output signal of the equalizer, select an operating mode of the equalizer from a plurality of different operating modes based on the determined signal metric, and control the equalizer to operate in the selected operating mode.

公开(公告)号：US20220337292A1

公开(公告)日：2022-10-20

申请号：US17763209

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Sanket JAIN ,  Benjamin JANN ,  Ashoke RAVI ,  Satwik PATNAIK

IPC: H04B7/0413 ,  H04B7/26 ,  H04B7/01

Abstract: A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.