公开(公告)号：US20230369503A1

公开(公告)日：2023-11-16

申请号：US17742664

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Cheng Tan ,  Van H. Le ,  Akash Garg ,  Shokir A. Pardaev ,  Timothy Jen ,  Abhishek Anil Sharma ,  Thiruselvam Ponnusamy ,  Moira C. Vyner ,  Caleb Barrett ,  Forough Mahmoudabadi ,  Albert B. Chen ,  Travis W. Lajoie ,  Christopher M. Pelto

IPC: H01L29/786 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L29/78618 ,  H01L23/5226 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

公开(公告)号：US20230395506A1

公开(公告)日：2023-12-07

申请号：US17833708

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Miriam Reshotko ,  Elijah Karpov ,  Mark Anders ,  Gauri Auluck ,  Shakuntala Sundararajan ,  Michael Makowski ,  Caleb Barrett

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53266

Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

公开(公告)号：US11532619B2

公开(公告)日：2022-12-20

申请号：US16367175

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Jack Kavalieros ,  Caleb Barrett ,  Jay P. Gupta ,  Nishant Gupta ,  Kaiwen Hsu ,  Byungki Jung ,  Aravind S. Killampalli ,  Justin Railsback ,  Supanee Sukrittanon ,  Prashant Wadhwa

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/423

Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.