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    Modular technique for die-level liquid cooling
    1.
    发明授权
    Modular technique for die-level liquid cooling 有权

    公开(公告)号：US11508645B2

    公开(公告)日：2022-11-22

    申请号：US16636296

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Chandra M. Jha ,  Je-Young Chang

    IPC: H01L23/473 ,  H01L23/373 ,  H01L23/40

    Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.

    Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging
    2.
    发明授权
    Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging 有权

    公开(公告)号：US10607909B2

    公开(公告)日：2020-03-31

    申请号：US16075120

    申请日：2016-04-02

    Applicant: Intel Corporation

    Inventor： Purushotham Kaushik Muthur Srinath ,  Pramod Malatkar ,  Sairam Agraharam ,  Chandra M. Jha ,  Arnab Choudhury ,  Nachiket R. Raravikar

    IPC: H01L23/367 ,  H01L23/26 ,  H01L23/433 ,  H01L25/065 ,  H01L23/36 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

    Architecture material and process to improve thermal performance of the embedded die package
    4.
    发明授权
    Architecture material and process to improve thermal performance of the embedded die package 有权

    公开(公告)号：US10121722B1

    公开(公告)日：2018-11-06

    申请号：US15721880

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Chandra M. Jha ,  Eric J. Li ,  Zhaozhi Li ,  Robert M. Nickerson

    IPC: H01L23/34 ,  H01L23/373 ,  H01L23/00

    Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.

    THERMAL INTERFACES FOR INTEGRATED CIRCUIT PACKAGES
    6.
    发明申请
    THERMAL INTERFACES FOR INTEGRATED CIRCUIT PACKAGES 审中-公开

    公开(公告)号：US20180090411A1

    公开(公告)日：2018-03-29

    申请号：US15279222

    申请日：2016-09-28

    Applicant: Intel Corporation

    Inventor： Edvin Cetegen ,  Omkar G. Karhade ,  Kedar Dhane ,  Chandra M. Jha

    IPC: H01L23/367 ,  H01L23/373

    CPC classification number: H01L23/3736 ,  H01L23/3733 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433

    Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

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