公开(公告)号：US10409727B2

公开(公告)日：2019-09-10

申请号：US15475249

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Rajat Agarwal ,  Jong Soo Park ,  Christopher J. Hughes ,  Chiachen Chou

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/04 ,  G06F12/0831 ,  G06F12/0886

Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

公开(公告)号：US20190004955A1

公开(公告)日：2019-01-03

申请号：US15640534

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Michael C. Adler ,  Chiachen Chou ,  Neal C. Crago ,  Kermin Fleming ,  Kent D. Glossop ,  Aamer Jaleel ,  Pratik M. Marolia ,  Simon C. Steely, JR. ,  Samantika S. Sury

IPC: G06F12/0862 ,  G06F12/0802 ,  H03K19/177 ,  G06F15/78

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F15/7867 ,  G06F15/8015 ,  G06F17/505 ,  G06F2212/6026 ,  G11C8/12 ,  H03K19/17736 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

公开(公告)号：US11030108B2

公开(公告)日：2021-06-08

申请号：US16540163

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Rajat Agarwal ,  Jong Soo Park ,  Christopher J. Hughes ,  Chiachen Chou

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0886

Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

公开(公告)号：US10387319B2

公开(公告)日：2019-08-20

申请号：US15640534

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Michael C. Adler ,  Chiachen Chou ,  Neal C. Crago ,  Kermin Fleming ,  Kent D. Glossop ,  Aamer Jaleel ,  Pratik M. Marolia ,  Simon C. Steely, Jr. ,  Samantika S. Sury

IPC: G06F12/0802 ,  G06F15/00 ,  G06F12/0862 ,  H03K19/177 ,  G06F15/78 ,  G11C8/12 ,  G06F17/50 ,  G06F15/80

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.