公开(公告)号：US20240114696A1

公开(公告)日：2024-04-04

申请号：US17957603

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher Neumann ,  Cory Weinstein ,  Nazila Haratipour ,  Brian Doyle ,  Sou-Chi Chang ,  Tristan Tronic ,  Shriram Shivaraman ,  Uygar Avci

IPC: H01L27/11507 ,  H01L27/11514

CPC classification number: H01L27/11507 ,  H01L27/11514

Abstract: Multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. Insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. Wider portions of an inner plate may be formed in lateral recesses between insulating layers. Ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. An etch-stop layer may protect the inner plate when sacrificial layers are removed. An etch-stop or interface layer may remain over the inner plate adjacent insulators.

公开(公告)号：US20240114695A1

公开(公告)日：2024-04-04

申请号：US17957560

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Christopher Neumann ,  Shriram Shivaraman ,  Brian Doyle ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. A capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. The cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.

公开(公告)号：US20240112714A1

公开(公告)日：2024-04-04

申请号：US17957591

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Christopher Neumann ,  Brian Doyle ,  Sou-Chi Chang ,  Bernal Granados Alpizar ,  Sarah Atanasov ,  Matthew Metz ,  Uygar Avci ,  Jack Kavalieros ,  Shriram Shivaraman

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

CPC classification number: G11C11/221 ,  H01L27/11507 ,  H01L28/55

Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.