公开(公告)号：US20200313076A1

公开(公告)日：2020-10-01

申请号：US16367131

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Christopher WIEGAND ,  Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI

IPC: H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: A spin orbit memory device includes a first electrode including a beta-phase material. The spin orbit memory device further includes a material layer stack on a portion of the first electrode. The material layer stack includes a first layer on the first electrode, where the first layer includes a bcc material such as molybdenum. The material layer stack further includes layers of a perpendicular magnetic tunnel junction (pMTJ) device on the first layer. The pMTJ device includes a free magnet structure on the first layer, where the free magnet structure includes a first magnet and a second magnet on the first magnet. The pMTJ device further includes a fixed magnet above the free magnet structure and a tunnel barrier layer between the magnet structure and the third magnet and a second electrode coupled with the second magnet.

公开(公告)号：US20200006637A1

公开(公告)日：2020-01-02

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Christopher WIEGAND ,  Angeline SMITH ,  Noriyuki SATO ,  Kevin O'BRIEN ,  Benjamin BUFORD ,  Ian YOUNG ,  MD Tofizur RAHMAN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20200313075A1

公开(公告)日：2020-10-01

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Kevin O'Brien ,  Benjamin BUFORD ,  Tofizur RAHMAN ,  Rohan PATIL ,  Nafees KABIR ,  Michael CHRISTENSON ,  Ian YOUNG ,  Hui Jae YOO ,  Christopher WIEGAND

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US20200312908A1

公开(公告)日：2020-10-01

申请号：US16367133

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Christopher WIEGAND ,  Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI

IPC: H01L27/22 ,  H01L43/14

Abstract: A spin orbit memory device includes a material layer stack on a spin orbit electrode. The material layer stack includes a magnetic tunnel junction (MTJ) and a synthetic antiferromagnetic (SAF) structure on the MTJ. The SAF structure includes a first magnet structure and a second magnet structure separated by an antiferromagnetic coupling layer. The first magnet structure includes a first magnet and a second magnet separated by a single layer of a non-magnetic material such as platinum. The second magnet structure includes a stack of bilayers, where each bilayer includes a layer of platinum on a layer of a magnetic material such.

公开(公告)号：US20220140230A1

公开(公告)日：2022-05-05

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20200303623A1

公开(公告)日：2020-09-24

申请号：US16358671

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Christopher WIEGAND ,  Gokul MALYAVANATHAM ,  Oleg GOLONZKA

IPC: H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  H01L43/12

Abstract: An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.

公开(公告)号：US20200083427A1

公开(公告)日：2020-03-12

申请号：US16128426

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20190280188A1

公开(公告)日：2019-09-12

申请号：US16348364

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Justin BROCKMAN ,  Christopher WIEGAND ,  MD Tofizur RAHMAN ,  Daniel OUELETTE ,  Angeline SMITH ,  Juan ALZATE VINASCO ,  Charles KUO ,  Mark DOCZY ,  Kaan OGUZ ,  Kevin O'BRIEN ,  Brian DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.