公开(公告)号：US20180129180A1

公开(公告)日：2018-05-10

申请号：US15729618

申请日：2017-10-10

Applicant: Intel Corporation

Inventor： Craig S. Forbell

IPC: G05B19/042

CPC classification number: G05B19/0428 ,  G05B2219/24205

Abstract: Particular embodiments described herein provide for a system, such as a computing system, that includes a processor operable to execute instructions associated with the electronic code, a thermal sensor operable to measure a temperature associated with a device, and a controller in communication with the thermal sensor. The controller is configured to receive an activity status associated with the processor, and receiving a temperature output value representative of a measured temperature associated with the device from the thermal sensor. The controller is further configured to provide a disable signal to the thermal sensor based upon the activity status indicating that the processor is in a reduced activity state and that the temperature output value is less than or equal to a predetermined temperature threshold value.

公开(公告)号：US09785136B2

公开(公告)日：2017-10-10

申请号：US13631985

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Craig S. Forbell

IPC: G05B11/01 ,  G05B19/042

CPC classification number: G05B19/0428 ,  G05B2219/24205

Abstract: Particular embodiments described herein provide for a system, such as a computing system, that includes a processor operable to execute instructions associated with the electronic code, a thermal sensor operable to measure a temperature associated with a device, and a controller in communication with the thermal sensor. The controller is configured to receive an activity status associated with the processor, and receiving a temperature output value representative of a measured temperature associated with the device from the thermal sensor. The controller is further configured to provide a disable signal to the thermal sensor based upon the activity status indicating that the processor is in a reduced activity state and that the temperature output value is less than or equal to a predetermined temperature threshold value.

公开(公告)号：US20160041595A1

公开(公告)日：2016-02-11

申请号：US14919780

申请日：2015-10-22

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jeffrey R. Wilcox ,  Michael N. Derr ,  Neil W. Songer ,  Craig S. Forbell

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.