公开(公告)号：US20240220446A1

公开(公告)日：2024-07-04

申请号：US18149072

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Zhongsheng Wang ,  Russell Fenger ,  Asit Kumar Verma ,  DK Deepika ,  Yevgeni Sabin ,  Daniel J. Rogers ,  Cameron T. Rieck

IPC: G06F15/80 ,  G06F9/48

CPC classification number: G06F15/80 ,  G06F9/48

Abstract: Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).