公开(公告)号：US09785576B2

公开(公告)日：2017-10-10

申请号：US14227178

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Thiam Wah Loh ,  Per Hammarlund ,  Andreas Wasserbauer ,  Swee Chong Peter Kuan ,  Eckhard Delfs ,  Deepak A. Mathaikutty ,  Stephen J. Robinson ,  Gautham N. Chinya ,  Perry H. Wang ,  Chee Weng Tan ,  Hong Wang ,  Reza Fortas

IPC: G06F12/14 ,  G11C29/52 ,  G06F21/57 ,  G11C7/10 ,  G06F21/10

CPC classification number: G06F12/1408 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/032 ,  Y02D10/13

Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

公开(公告)号：US11010166B2

公开(公告)日：2021-05-18

申请号：US15087854

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Debabrata Mohapatra ,  Perry H. Wang ,  Xiang Zou ,  Sang Kyun Kim ,  Deepak A. Mathaikutty ,  Gautham N. Chinya

IPC: G06F9/302 ,  G06F9/318 ,  G06F9/30

Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

公开(公告)号：US20170286117A1

公开(公告)日：2017-10-05

申请号：US15087854

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Debabrata Mohapatra ,  Perry H. Wang ,  Xiang Zou ,  Sang Kyun Kim ,  Deepak A. Mathaikutty ,  Gautham N. Chinya

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3873

Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

公开(公告)号：US09003164B2

公开(公告)日：2015-04-07

申请号：US14221741

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Gautham N. Chinya ,  Hong Wang ,  Deepak A. Mathaikutty ,  Jamison D. Collins ,  Ethan Schuchman ,  James P. Held ,  Ajay V. Bhatt ,  Prashant Sethi ,  Stephen F. Whalley

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/254

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程 记忆。 以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。 描述和要求保护其他实施例。