公开(公告)号：US20230229594A1

公开(公告)日：2023-07-20

申请号：US18092278

申请日：2022-12-31

Applicant: Intel Corporation

Inventor： Kai CHENG ,  Divya GUPTA ,  Nikethan Shivanand BALIGAR ,  Vivek GARG ,  Aurelio RODRIGUEZ ECHEVARRIA ,  Russell J. WUNDERLICH

IPC: G06F12/0804 ,  G11C5/14

CPC classification number: G06F12/0804 ,  G11C5/141

Abstract: A system detects a powerdown event, such as a power loss event, and performs a flush of volatile memory to persistent memory during a powerdown sequence. The system includes an energy backup device to power the system during the powerdown sequence. The system is configurable with optional settings that configure the powerdown sequence specific to a type of the energy backup device.

公开(公告)号：US20240289202A1

公开(公告)日：2024-08-29

申请号：US18656375

申请日：2024-05-06

Applicant: Intel Corporation

Inventor： Divya GUPTA ,  Raed AL-OMARI ,  Yi ZENG ,  Sheng HUANG

IPC: G06F11/07 ,  G06F9/4401 ,  G06F13/42

CPC classification number: G06F11/0787 ,  G06F9/4401 ,  G06F13/4282 ,  G06F2213/0002

Abstract: Examples described herein relate to a bootable processor that comprises circuitry to load boot firmware. The bootable processor can execute a firmware that is to collect an error log of an error during boot of the bootable processor and that occurred prior to enablement of an Out of Band (OOB) manageability port. The firmware can cause output of the error log to a second circuitry through an interface that is operational prior to enablement of the OOB manageability port.

公开(公告)号：US20240211332A1

公开(公告)日：2024-06-27

申请号：US18596471

申请日：2024-03-05

Applicant: Intel Corporation

Inventor： Divya GUPTA ,  Shubhada PUGAONKAR ,  Raed AL-OMARI ,  Mariecel TORRES-YOUNG ,  Ayman G. ABDO ,  John R. AYERS ,  Chih-Cheh CHEN ,  Wilfredo FIGUEROA MARTINEZ ,  Girish CHANDRASEKARAN

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0757 ,  G06F11/0778

Abstract: Examples include techniques to collecting and providing error related information for a multi-die system-on-a-chip (SOC) computing system following a critical or catastrophic error. Examples include circuitry on a first die that is configured to receive an indication of a critical or catastrophic error and cause error related information to be stored to a volatile memory at the first die that is arranged to continually maintain power during a global reset of the SOC. The circuitry can also be configured to provide the stored error related information to a requestor following the global reset of the SOC.