公开(公告)号：US20230096451A1

公开(公告)日：2023-03-30

申请号：US17484193

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Salma Johnson ,  Duane Galbi ,  Bradley Burres ,  Jose Niell ,  Jeongnim Kim ,  Reshma Lal ,  Anandhi Jayakumar ,  Mrittika Ganguli ,  Thomas Willis

IPC: G06F9/50 ,  H04L29/08 ,  H04L29/06 ,  H04L9/08

Abstract: Techniques for remote disaggregated infrastructure processing units (IPUs) are described. An apparatus described herein includes an interconnect controller to receive a transaction layer packet (TLP) from a host compute node; identify a sender and a destination from the TLP; and provide, to a content addressable memory (CAM), a key determined from the sender and the destination. The apparatus as described herein can further include core circuitry communicably coupled to the interconnect controller, the core circuitry to determine an output of the CAM based on the key, the output comprising a network address of an infrastructure processing unit (IPU) assigned to the host compute node, wherein the IPU is disaggregated from the host compute node over a network; and send the TLP to the IPU using a transport protocol.

公开(公告)号：US20230029026A1

公开(公告)日：2023-01-26

申请号：US17958140

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Andrzej Kuriata ,  Duane Galbi

IPC: G06F13/40 ,  H04L67/2866

Abstract: A network processing device connects to one or more devices in a computing node and connects to one or more other network processing devices of other computing nodes. The network processing device identifies a policy for allowing devices in other computing nodes to access a particular resource of one of the devices in its computing node. The network processing device receives an access request to access the particular resource from another network processing device and sends a request to the device hosting the particular resource based on the access request and the policy.

公开(公告)号：US10884968B2

公开(公告)日：2021-01-05

申请号：US16366496

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Bradley Burres ,  Duane Galbi ,  Amit Kumar ,  Yadong Li ,  Salma Mirza ,  Jose Niell ,  Thomas E. Willis ,  William Duggan

IPC: G06F13/42 ,  G06F8/60

Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.

公开(公告)号：US20230185658A1

公开(公告)日：2023-06-15

申请号：US18108470

申请日：2023-02-10

Applicant: Intel Corporation

Inventor： Duane Galbi ,  Matthew Adiletta

IPC: G06F11/07 ,  G06F12/0811

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F12/0811 ,  G06F2212/601

Abstract: An example of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory for a range of addresses within a memory address space, configure a first region of the memory within a first sub-range of addresses within the memory address space to be accessed with a first protection level of two or more memory fault protection levels, and configure a second region of the memory within a second sub-range of addresses within the memory address space that is non-overlapping with the first sub-range to be accessed with a second protection level of the two or more memory fault protection levels. Other examples are disclosed and claimed.

公开(公告)号：US10783100B2

公开(公告)日：2020-09-22

申请号：US16366504

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Brad Burres ,  Duane Galbi ,  Amit Kumar ,  Yadong Li ,  Salma Mirza ,  Jose Niell ,  Thomas E. Willis ,  William Duggan

IPC: G06F13/20 ,  G06F13/42

Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.