公开(公告)号：US11737253B2

公开(公告)日：2023-08-22

申请号：US16605903

申请日：2017-06-22

Applicant: Intel Corporation

Inventor： Zheng Guo ,  Clifford L. Ong ,  Eric A. Karl ,  Mark T. Bohr

IPC: H10B10/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

CPC classification number: H10B10/12 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

公开(公告)号：US20200286549A1

公开(公告)日：2020-09-10

申请号：US16827526

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Zheng Guo ,  Clifford L. Ong ,  Eric A. Karl

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C5/06 ,  G11C11/408 ,  G11C5/02 ,  H01L27/11

Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.

公开(公告)号：US12171090B2

公开(公告)日：2024-12-17

申请号：US18209988

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Zheng Guo ,  Clifford L. Ong ,  Eric A. Karl ,  Mark T. Bohr

IPC: H10B10/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

公开(公告)号：US20230209799A1

公开(公告)日：2023-06-29

申请号：US17560927

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Dan Lavric ,  Leonard Guler ,  YenTing Chiu ,  Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L29/4908 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/78696 ,  H01L29/6684 ,  H01L29/66742

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：US20220253285A1

公开(公告)日：2022-08-11

申请号：US17730011

申请日：2022-04-26

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Clifford Lu Ong ,  Dmitri E. Nikonov ,  Ian A. Young ,  Eric A. Karl

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/22 ,  G06N3/04

Abstract: An analog multiplication circuit includes switched capacitors to multiply digital operands in an analog representation and output a digital result with an analog-to-digital convertor. The capacitors are arranged with a capacitance according to the respective value of the digital bit inputs. To perform the multiplication, the capacitors are selectively charged according to the first operand of the multiplication. The capacitors are then connected to a common interconnect for charge sharing across the capacitors, averaging the charge according to the charge determined by the first operand. The capacitor are then maintained or discharged according to a second operand, such that the remaining charge represents a number of “copies” of the averaged charge. The capacitors are then averaged and output for conversion by an analog-to-digital convertor. This circuit may be repeated to construct a multiply-and-accumulate circuit by combining charges from several such multiplication circuits.

公开(公告)号：US11205616B2

公开(公告)日：2021-12-21

申请号：US16604807

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US12224239B2

公开(公告)日：2025-02-11

申请号：US18599049

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20210098059A1

公开(公告)日：2021-04-01

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/56 ,  G11C7/10 ,  G06F3/06

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US10957386B2

公开(公告)日：2021-03-23

申请号：US16827526

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Zheng Guo ,  Clifford L. Ong ,  Eric A. Karl

IPC: G11C5/14 ,  G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C5/06 ,  G11C11/408 ,  G11C5/02 ,  H01L27/11 ,  G06F30/392

Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.

公开(公告)号：US20190272868A1

公开(公告)日：2019-09-05

申请号：US15909284

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： Zheng Guo ,  Clifford L. Ong ,  Eric A. Karl

IPC: G11C11/419 ,  G11C5/14 ,  G11C5/06 ,  G11C7/12 ,  G11C7/22

Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.