公开(公告)号：US20240291786A1

公开(公告)日：2024-08-29

申请号：US18660020

申请日：2024-05-09

Applicant: Intel Corporation

Inventor： Janusz P. Jurski ,  Mariusz Oriol ,  Filip Schmole

IPC: H04L51/21 ,  H04L45/02

CPC classification number: H04L51/21 ,  H04L45/02

Abstract: A management control message is received to be routed from a first device to a second device in a system. The management control message is determined to include management control data. It is determined whether the second device supports such management control messages and it is determined whether to forward the management control message to the second device based on whether the second device supports management control messages. Management control messages are routed to destination devices within the system over a bridge device associated with the management control messages.

公开(公告)号：US12248561B2

公开(公告)日：2025-03-11

申请号：US17485421

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Ravi Sahita ,  Utkarsh Y KAKAIYA ,  Abhishek Basak ,  Lee Albion ,  Filip Schmole ,  Rupin Vakharwala ,  Vinit M Abraham ,  Raghunandan Makaram

IPC: G06F21/54 ,  G06F9/455 ,  G06F13/40 ,  G06F21/56

Abstract: Apparatus and method for role-based register protection. For example, one embodiment of an apparatus comprises: one or more processor cores to execute instructions and process data, the one or more processor cores to execute one or more security instructions to protect a virtual machine or trusted application from a virtual machine monitor (VMM) or operating system (OS); an interconnect fabric to couple the one or more processor cores to a device; and security hardware logic to determine whether to allow a read or write transaction directed to a protected register to proceed over the interconnect fabric, the security hardware logic to evaluate one or more security attributes associated with an initiator of the transaction to make the determination.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US20230136091A1

公开(公告)日：2023-05-04

申请号：US18148478

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Kapil Karkra ,  Filip Schmole ,  Pankaj Kumar

IPC: G06F9/46

Abstract: Technology described herein provides an improved system architecture for offloading infrastructure tasks using a multi-root switch with logic to route, via a switch, application data in a data transfer message between a physical storage device and a host system, the host system interfacing with a virtual function of an IPU, by remapping a transaction identifier field in the data transfer message between a first transaction identifier associated with the virtual function and a second transaction identifier associated with the physical storage device, where the physical storage device is managed by the IPU, and where to route the application data between the host system and the physical storage device includes to bypass temporary storage of the application data in a memory local to the IPU. In some examples a remapping table holds the first transaction identifier and the second transaction identifier.

公开(公告)号：US11216396B2

公开(公告)日：2022-01-04

申请号：US15280730

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Raj K. Ramanujan ,  Filip Schmole ,  David M. Lee ,  Ishwar Agarwal ,  David J. Harriman

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F12/12

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.

公开(公告)号：US20180089115A1

公开(公告)日：2018-03-29

申请号：US15280730

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Raj K. Ramanujan ,  Filip Schmole ,  David M. Lee ,  Ishwar Agarwal ,  David J. Harriman

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F12/128

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/12 ,  G06F13/4282

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.