公开(公告)号：US20230197714A1

公开(公告)日：2023-06-22

申请号：US17556614

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Aryan NAVABI-SHIRAZI ,  Andy Chih-Hung WEI ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Pratik PATEL

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/40

CPC classification number: H01L27/088 ,  H01L27/1203 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401

Abstract: Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures.

公开(公告)号：US20220199774A1

公开(公告)日：2022-06-23

申请号：US17131622

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Andy Chih-Hung WEI ,  Guillaume BOUCHE ,  Jack T. KAVALIEROS

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088

Abstract: Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.

公开(公告)号：US20250113581A1

公开(公告)日：2025-04-03

申请号：US18374599

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Hwichan JUN ,  Guillaume BOUCHE ,  Sudipto NASKAR

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Trench contact structures with airgap spacers, and methods of fabricating trench contact structures with airgap spacers, are described. In an example, an integrated circuit structure includes a fin structure or a nanowire structure. An epitaxial source or drain structure is on the fin structure or the nanowire structure. A gate structure is over the fin structure or around the nanowire structure. A trench contact structure is laterally spaced apart from the gate structure and coupled to the epitaxial source or drain structure. A trench contact spacer is adjacent to sidewalls of the trench contact structure, the trench contact spacer including an outer spacer portion, an airgap, and an inner spacer portion.

公开(公告)号：US20220415796A1

公开(公告)日：2022-12-29

申请号：US17359434

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Andy Chih-Hung WEI ,  Guillaume BOUCHE

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/308

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a buried power rail (BPR) located within the transistor structure at a level below a height of one or more of the fins of the transistor structure. The BPR may be located proximate to a bottom substrate of the transistor structure. In embodiments, the transistor structure includes a protective layer, which can include one or more dielectric layers, above the BPR to protect the BPR during stages of transistor structure manufacture. In embodiments, portions of the protective layer may also be used to constrain epitaxial growth during stages of manufacturing of the transistor structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20220416057A1

公开(公告)日：2022-12-29

申请号：US17358559

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Shashi VYAS ,  Andy Chih-Hung WEI ,  Leonard P. GULER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L21/28 ,  H01L21/8234

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to manufacturing a gate structure that includes adjacent gates that are coupled with the first fin and a second fin, with a metal gate cut across the adjacent gates and a trench connector between the adjacent gates that electrically couples the first fin and the second fin. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197713A1

公开(公告)日：2023-06-22

申请号：US17554442

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Andy Chih-Hung WEI ,  Anand S. MURTHY ,  Aryan NAVABI-SHIRAZI ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823814 ,  H01L21/823412 ,  H01L27/092 ,  H01L21/823481 ,  H01L21/823418

Abstract: Gate-all-around integrated circuit structures having raised wall structures for epitaxial source or drain region confinement are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface above a top surface of the first and second vertical arrangements of nanowires. The intervening dielectric structure has a width at the top surface of the intervening dielectric structure less than a width below the top surface of the intervening dielectric structure.

公开(公告)号：US20220415736A1

公开(公告)日：2022-12-29

申请号：US17356036

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Shashi VYAS ,  Andy Chih-Hung WEI ,  Charles H. WALLACE ,  Sachin PANDIJA

IPC: H01L23/29 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L23/31 ,  H01L21/56 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197819A1

公开(公告)日：2023-06-22

申请号：US17559903

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Andy Chih-Hung WEI

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

Abstract: Integrated circuit structures having a metal gate plug landed on a dielectric dummy fin, and methods of fabricating integrated circuit structures having a metal gate plug landed on a dielectric dummy fin, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric dummy fin is laterally spaced apart from the plurality of horizontally stacked nanowires, the dielectric dummy fin having a bottommost surface below an uppermost surface of the sub-fin. A dielectric gate plug is on the dielectric dummy fin.