公开(公告)号：US20230207486A1

公开(公告)日：2023-06-29

申请号：US17561833

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Gwang-Soo Kim ,  Dimitrios Antartis ,  Han Ju Lee ,  Christopher Pelto

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/76802 ,  H01L21/76877

Abstract: An integrated circuit (IC) die comprises a first metallization layer comprising first interconnect structures which each extend through the first metallization layer, a second metallization layer comprising second interconnect structures which each extend through the second metallization layer, an interlayer dielectric (ILD) stack between the first metallization layer and the second metallization layer. The ILD stack comprises a stress modulation layer on the first metallization layer and a capping layer on the stress modulation layer. A first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer.

公开(公告)号：US20250112168A1

公开(公告)日：2025-04-03

申请号：US18477813

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Gwang-Soo Kim ,  Harini Kilambi ,  Han Ju Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: Alignment markers are created on a carrier wafer prior to attachment of integrated circuit dies to the carrier wafer. The alignment markers can be used in aligning integrated circuit dies to the carrier wafer during attachment of the integrated circuit dies to the carrier wafer. A reconstituted wafer can be created from the integrated circuit dies attached to the carrier wafer and the alignment markers are part of the reconstituted wafer. The alignment markers can further be used to align a wafer bonding layer to the reconstituted wafer. The wafer bonding layer can be used in attaching the reconstituted wafer to an interposer, another wafer, or another microelectronic structure. The alignment markers are located outside an outer lateral boundary of the integrated circuit dies (such as between integrated circuit dies) and are not connected to any metal lines in the integrated circuit dies in the reconstituted wafer.