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公开(公告)号:US20230350131A1
公开(公告)日:2023-11-02
申请号:US17733302
申请日:2022-04-29
Applicant: Intel Corporation
Inventor: Hiroki Tanaka , Bai Nie , Kristof Darmawikarta , Hari Mahalingam
CPC classification number: G02B6/122 , G02B6/30 , G02B2006/12121
Abstract: Techniques for signal amplification for a photonic integrated circuit (PIC) die are disclosed. In the illustrative embodiment, an optical fiber is coupled to an input signal waveguide in a glass interposer, and an input signal waveguide of a PIC die is coupled to the input signal waveguide of the glass interposer. In order to compensate for any coupling losses, the input signal waveguide of the glass interposer is active, amplifying an input signal. Light in a pump waveguide near the input signal waveguide pumps ions in the input signal waveguide into a population inversion, allowing them to amplify the input signal.
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公开(公告)号:US20240361541A1
公开(公告)日:2024-10-31
申请号:US18309123
申请日:2023-04-28
Applicant: Intel Corporation
Inventor: Alexander Krichevsky , Boping Xie , Sunil Priyadarshi , Chao Tian , Guojiang Hu , Hari Mahalingam , Haijiang Yu
IPC: G02B6/42
CPC classification number: G02B6/4206 , G02B6/42 , G02B6/4214
Abstract: Method and apparatus for vision assisted optical alignment. In the apparatus, one or more main waveguides of a photonic integrated circuit (PIC) are selected, and respective one or more corresponding auxiliary waveguides are terminated with a respective scattering structure. The scattering structures deflect externally supplied light out of the PIC for detection by a camera or photo detector to provide feedback on the amount of light coupled into the main waveguides during the optical alignment process. The method and apparatus eliminate the need to power up the PIC circuitry, speed up the subsequent alignment process, and allow control and failure analysis of multiple channels at once.
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公开(公告)号:US20230076917A1
公开(公告)日:2023-03-09
申请号:US17470684
申请日:2021-09-09
Applicant: Intel Corporation
Inventor: Hiroki Tanaka , Brandon C. Marin , Kristof Darmawikarta , Srinivas Venkata Ramanuja Pietambaram , Jeremy D. Ecton , Hari Mahalingam , Benjamin Duong
IPC: G02F1/035
Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
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公开(公告)号:US20220413213A1
公开(公告)日:2022-12-29
申请号:US17358912
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Harel Frish , John Heck , Randal Appleton , Stefan Meister , Haisheng Rong , Joshua Keener , Michael Favaro , Wesley Harrison , Hari Mahalingam , Sergei Sochava
Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.
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公开(公告)号:US20190121036A1
公开(公告)日:2019-04-25
申请号:US16225248
申请日:2018-12-19
Applicant: Intel Corporation
Inventor: John Heck , Hari Mahalingam , Paul Yu , Kumar Satya Harinadh Potluri
IPC: G02B6/42
Abstract: In various embodiments, optical fibers may be placed into V-shaped grooves in a substrate. A lid may then be placed on top of the optical fibers to hold them accurately in place, and the lid may be attached to the substrate using a reflow solder technique. Epoxy may then be applied as a strain relief. Because the V-shaped grooves and optical waveguides are manufactured with precision on the same substrate, precise alignment between these two may be achieved. Because the epoxy is applied after reflow, the epoxy may not be exposed to reflow temperatures, which might otherwise cause the epoxy to distort during the cure process.
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公开(公告)号:US20250102745A1
公开(公告)日:2025-03-27
申请号:US18475907
申请日:2023-09-27
Applicant: Intel Corporation
Inventor: Mohanraj Prabhugoud , David Shia , Hari Mahalingam , John M. Heck , John Robert Macdonald , Duncan Peter Dore , Eric J. M. Moret , Nicholas D. Psaila , Sang Yup Kim , Shane Kevin Yerkes , Harel Frish
IPC: G02B6/42
Abstract: In one embodiment, a device includes a fiber array unit (FAU) coupled to a photonics integrated circuit (PIC) die. The PIC die includes a cavity defined at an edge of the PIC die, with outer edges of the cavity being formed at an angle less than 90 degrees with respect to a bottom surface of the cavity. The PIC die further includes first waveguides protruding into the cavity of the PIC die. The FAU includes a shelf portion extending from a body portion, and a plurality of second waveguides protruding from an outer edge of the shelf portion opposite the body portion. The FAU further includes alignment structures on outer edges of the shelf portion that are in contact with the angled edges of the cavity of the PIC die.
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公开(公告)号:US12216158B2
公开(公告)日:2025-02-04
申请号:US17102891
申请日:2020-11-24
Applicant: Intel Corporation
Inventor: Jeremy Hicks , Hari Mahalingam , Christopher Seibert , Eric Snow , Harel Frish
IPC: G01R31/311 , G02B6/30 , G02B6/42
Abstract: Systems and methods for testing a photonic IC (PIC) with an optical probe having an out-of-plane edge coupler to convey test signals between the out-of-plane probe and an edge coupled photonic waveguide within a plane of the PIC. To accommodate dimensions of the optical probe, a test trench may be fabricated in the PIC near an edge coupler of the waveguide. The optical probe may be displaced along one or more axes relative to a prober to position a free end of the prober within the test trench and to align the probe's out-of-plane edge coupler with an edge coupler of a PIC waveguide. Accordingly, a PIC may be probed at the wafer-level, without first dicing a wafer into PIC chips or bars. The optical probe may be physically coupled to a prober through a contact sensor to detect and/or avoid physical contact between probe and PIC.
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公开(公告)号:US20230204877A1
公开(公告)日:2023-06-29
申请号:US17561694
申请日:2021-12-23
Applicant: Intel Corporation
Inventor: John M. Heck , Haisheng Rong , Harel Frish , Ankur Agrawal , Boping Xie , Randal S. Appleton , Hari Mahalingam , Alexander Krichevsky , Pooya Tadayon , Ling Liao , Eric J. M. Moret
IPC: G02B6/42
CPC classification number: G02B6/4207 , G02B6/4214 , G02B6/428
Abstract: Technologies for beam expansion and collimation for photonic integrated circuits (PICs) are disclosed. In one embodiment, an ancillary die is bonded to a PIC die. Vertical couplers in the PIC die direct light from waveguides to flat mirrors on a top side of the ancillary die. The flat mirrors reflect the light towards curved mirrors defined in the bottom surface of the ancillary die. The curved mirrors collimate the light from the waveguides. In another embodiment, a cavity is formed in a PIC die, and curved mirrors are formed in the cavity. Light beams from waveguides in the PIC die are directed to the curved mirrors, which collimate the light beams.
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公开(公告)号:US20190339466A1
公开(公告)日:2019-11-07
申请号:US16517159
申请日:2019-07-19
Applicant: Intel Corporation
Inventor: John Heck , Harel Frish , Reece DeFrees , George A. Ghiurcan , Hari Mahalingam , Pegah Seddighian
IPC: G02B6/42
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for an optical coupler including an optical waveguide to guide light to an optical fiber. In embodiments, the optical waveguide includes a tapered segment to propagate the received light to the optical fiber. In embodiments, the tapered segment is buried below a surface of a semiconductor substrate to transition the received light within the semiconductor substrate from a first optical mode to a second optical mode to reduce a loss of light during propagation of the received light from the optical waveguide to the optical fiber. In embodiments, the surface of the semiconductor substrate comprises a bottom planar surface of a silicon photonic chip that includes at least one or more of passive or active photonic components. Other embodiments may be described and/or claimed.
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公开(公告)号:US12197004B2
公开(公告)日:2025-01-14
申请号:US17358912
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Harel Frish , John Heck , Randal Appleton , Stefan Meister , Haisheng Rong , Joshua Keener , Michael Favaro , Wesley Harrison , Hari Mahalingam , Sergei Sochava
Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.
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