公开(公告)号：US20240303195A1

公开(公告)日：2024-09-12

申请号：US18562743

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Keqiang Wu ,  Lingxiang Xiang ,  Heidi Pan ,  Christopher J. Hughes ,  Zhe Wang

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0891

CPC classification number: G06F12/0835 ,  G06F12/084 ,  G06F12/0891

Abstract: In one embodiment, a processor includes interconnect circuitry, processing circuitry, a first cache, and cache controller circuitry. The interconnect circuitry communicates over a processor interconnect with a second processor that includes a second cache. The processing circuitry generates a memory read request for a corresponding memory address of a memory. Based on the memory read request, the cache controller circuitry detects a cache miss in the first cache, which indicates that the first cache does not contain a valid copy of data for the corresponding memory address. Based on the cache miss, the cache controller circuitry requests the data from the second cache or the memory based on a current bandwidth utilization of the processor interconnect.