公开(公告)号：US20210286626A1

公开(公告)日：2021-09-16

申请号：US17213453

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US11537403B2

公开(公告)日：2022-12-27

申请号：US17213453

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US11640297B2

公开(公告)日：2023-05-02

申请号：US17304153

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Ashutosh Garg ,  Chandra S. Gurram ,  Jorge E. Parra ,  Junjie Gu ,  Konrad Trifunovic ,  Hong Bin Liao ,  Mike B. MacPherson ,  Shubh B. Shah ,  Shubra Marwaha ,  Stephen Junkins ,  Timothy R. Bauer ,  Varghese George ,  Weiyu Chen

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

公开(公告)号：US11042370B2

公开(公告)日：2021-06-22

申请号：US15957728

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Ashutosh Garg ,  Chandra S. Gurram ,  Jorge E. Parra ,  Junjie Gu ,  Konrad Trifunovic ,  Hong Bin Liao ,  Mike B. Macpherson ,  Shubh B. Shah ,  Shubra Marwaha ,  Stephen Junkins ,  Timothy R. Bauer ,  Varghese George ,  Weiyu Chen

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

公开(公告)号：US10990409B2

公开(公告)日：2021-04-27

申请号：US15493442

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.