公开(公告)号：US20170345496A1

公开(公告)日：2017-11-30

申请号：US15164665

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Daniel H. MORRIS ,  Sasikanth MANIPATRUNI ,  Kaushik VAIDYANATHAN ,  Ian A. YOUNG ,  Tanay KARNIK

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

Abstract: An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to be coupled to the select line during a first mode and to be de-coupled during a second mode.

公开(公告)号：US20190013063A1

公开(公告)日：2019-01-10

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Sasikanth MANIPATRUNI ,  Daniel H. MORRIS ,  Kaushik VAIDYANATHAN ,  Niloy MUKHERJEE ,  Dmitri E. NIKONOV ,  Ian YOUNG ,  Tanay KARNIK

IPC: G11C11/413 ,  G11C11/412 ,  G11C13/00 ,  G11C14/00 ,  G11C7/10

CPC classification number: G11C11/413 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/20 ,  G11C11/412 ,  G11C13/0007 ,  G11C14/009 ,  G11C2213/70 ,  G11C2213/71

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20190034360A1

公开(公告)日：2019-01-31

申请号：US15660819

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Kaushik VAIDYANATHAN ,  Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG ,  Tanay KARNIK ,  Huichu LIU

IPC: G06F13/10 ,  G06F9/445 ,  G06F1/26

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.