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1.发明公开公开(公告)号：US20240152178A1
公开(公告)日：2024-05-09
申请号：US17983707
申请日：2022-11-09
Applicant: Intel Corporation
Inventor： Prashant D. CHAUDHARI , Jain PHILIP , Gregory BERGSCHNEIDER , Jeffery S. BOLES , Hema C. NALLURI , Josh B. MASTRONARDE
Abstract: A system that includes two or more processor circuitry components and a power management circuitry comprising timestamp generator circuitry. In some examples, the timestamp generator circuitry is to generate timestamp values based on a single clock source and provide generated timestamp values to the two or more processor circuitry components. In some examples, the two or more processor circuitry components share timestamp values and the two or more processor circuitry components are to generate performance data associated with a timestamp of the generated timestamp values.
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2.发明公开公开(公告)号：US20240045725A1
公开(公告)日：2024-02-08
申请号：US17881540
申请日：2022-08-04
Applicant: Intel Corporation
Inventor： Prashant CHAUDHARI , Jain PHILIP , James VALERIO , Murali RAMADOSS , Ankur SHAH , Jeffery S. BOLES , Aditya NAVALE
CPC classification number: G06F9/5044 , G06F9/45558 , G06F2009/4557 , G06F2009/45583
Abstract: Apparatus and method for concurrent performance monitoring. For example, one embodiment of an apparatus comprises: compute hardware logic to concurrently process a number of workloads, the compute hardware logic to be subdivided into a plurality of compute hardware contexts based on the number of workloads; and programmable performance monitoring circuitry to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier associated with each of the compute hardware contexts.
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