公开(公告)号：US20250147762A1

公开(公告)日：2025-05-08

申请号：US18504407

申请日：2023-11-08

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Gang Chen ,  Supratim Pal ,  Jorge Eduardo Parra Osorio ,  Arthur Hunter ,  Boris Kuznetsov ,  Deepak N K ,  Siva Kumar Seemakurthi ,  James Valerio ,  Shubham Dinesh Chavan ,  Abhishek Kumar Singh ,  Samir Pandya ,  Sandeep Tippannanavar Niranjan ,  Alan Curtis ,  Jain Philip ,  Maltesh Kulkarni ,  Fangwen Fu ,  John Wiegert ,  Brent Schwartz

IPC: G06F9/30 ,  G06T15/00

Abstract: Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.

公开(公告)号：US20240160478A1

公开(公告)日：2024-05-16

申请号：US17987185

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Chunhui Mei ,  Ben J. Ashbaugh ,  Naveen Matam ,  Joydeep Ray ,  Timothy Bauer ,  Guei-Yuan Lueh ,  Vasanth Ranganathan ,  Prashant Chaudhari ,  Vikranth Vemulapalli ,  Nishanth Reddy Pendluru ,  Piotr Reiter ,  Jain Philip ,  Marek Rudniewski ,  Christopher Spencer ,  Parth Damani ,  Prathamesh Raghunath Shinde ,  John Wiegert ,  Fataneh Ghodrat

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.