公开(公告)号：US10078363B2

公开(公告)日：2018-09-18

申请号：US14996941

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： James P. Kardach ,  Brian V. Belmont ,  Muthu K. Kumar ,  Riley W. Jackson ,  Gunner D. Danneels ,  Richard A. Forand ,  Vivek Gupta ,  Jeffrey L. Huckins ,  Kristoffer D. Fleming ,  Uma M. Gadamsetty

IPC: G06F12/00 ,  G06F1/32 ,  G06F13/40 ,  G10L19/04 ,  H04R1/10 ,  G06F1/26 ,  G06F13/10 ,  G06F7/00

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3293 ,  G06F13/102 ,  G06F13/4072 ,  G10L19/04 ,  H04R1/1091 ,  H04R2201/109 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D50/20

Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.

公开(公告)号：US20150178098A1

公开(公告)日：2015-06-25

申请号：US14578885

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC: G06F9/44 ,  G06F1/32

CPC classification number: G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

公开(公告)号：US09384010B2

公开(公告)日：2016-07-05

申请号：US14578885

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC: G06F1/32 ,  G06F1/00 ,  G06F9/44 ,  G06F15/80 ,  G06F9/38 ,  G06F12/08 ,  G06F13/42

CPC classification number: G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

公开(公告)号：US09384009B2

公开(公告)日：2016-07-05

申请号：US14572366

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/44 ,  G06F15/80 ,  G06F9/38 ,  G06F12/08 ,  G06F13/42

CPC classification number: G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

公开(公告)号：US08949633B2

公开(公告)日：2015-02-03

申请号：US13938150

申请日：2013-07-09

Applicant: Intel Corporation

Inventor： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC: G06F1/00 ,  G06F1/32 ,  G06F15/80

CPC classification number: G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract translation: 本发明的实施例是用于动态地交换处理器核心的技术。 第一个核心有一个第一个指令集。 第一个核心以第一个性能级别执行程序。 当触发事件发生时，第一个内核停止执行程序。 第二核心具有与第一指令集兼容的第二指令集，并且具有与第一性能级别不同的第二性能级别。 当第一个核心执行程序时，第二个内核处于掉电状态。 在第一核心停止执行程序之后，电路对第二核心供电，使得第二核心继续在第二性能级别执行程序。

公开(公告)号：US20150100809A1

公开(公告)日：2015-04-09

申请号：US14572366

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC: G06F1/32 ,  G06F15/80 ,  G06F9/38 ,  G06F13/42 ,  G06F12/08

CPC classification number: G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

公开(公告)号：US08982488B2

公开(公告)日：2015-03-17

申请号：US13729221

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： James P. Kardach ,  Kirsty MacDonald ,  Peter Gibson

IPC: G11B19/28

CPC classification number: G11B19/28

Abstract: Various embodiments are generally directed recurringly cycling the driving of a platter media of a hard drive with a motor, allowing rotation of the platter media to slow only to a threshold rotational speed to balance power conservation with delays in accessing data. A method comprises driving platter media of a hard drive to rotate at a selected normal rotational speed, retrieving data stored on the platter media when the platter media rotates at the normal rotational speed, ceasing to drive the platter media to rotate to allow the platter media to rotate under rotational inertia imparted to the platter media, monitoring a current rotational speed of the platter media, and resuming driving the platter media to rotate based on the current rotational speed falling to a lower threshold rotational speed selected to be less than the normal rotational speed. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常定期循环利用电动机驱动硬盘驱动器的盘片介质，允许盘片介质的旋转仅减慢到阈值旋转速度以平衡功率节省与访问数据的延迟。 一种方法包括驱动硬盘驱动器的盘式介质以选定的正常转速旋转，当盘式介质以正常旋转速度旋转时检索存储在盘形介质上的数据，停止驱动盘式介质旋转以允许盘片介质 在旋转惯性下旋转到盘片介质上，监测盘片介质的当前旋转速度，并且基于当前旋转速度下降到低于正常旋转的较低阈值旋转速度，重新开始驱动盘片介质旋转 速度。 描述和要求保护其他实施例。

公开(公告)号：US20160132101A1

公开(公告)日：2016-05-12

申请号：US14996941

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： James P. Kardach ,  Brian V. Belmont ,  Muthu K. Kumar ,  Riley W. Jackson ,  Gunner D. Danneels ,  Richard A. Forand ,  Vivek Gupta ,  Jeffrey L. Huckins ,  Kristoffer D. Fleming ,  Uma M. Gadamsetty

IPC: G06F1/32 ,  G06F1/26 ,  G06F13/10

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3293 ,  G06F13/102 ,  G06F13/4072 ,  G10L19/04 ,  H04R1/1091 ,  H04R2201/109 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D50/20

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

公开(公告)号：US09305562B2

公开(公告)日：2016-04-05

申请号：US14691009

申请日：2015-04-20

Applicant: Intel Corporation

Inventor： James P. Kardach ,  Brian V. Belmont ,  Muthu K. Kumar ,  Riley W. Jackson ,  Gunner D. Danneels ,  Richard A. Forand ,  Vivek Gupta ,  Jeffrey L. Huckins ,  Kristoffer D. Fleming ,  Uma M. Gadamsetty

IPC: G06F12/00 ,  G10L19/04 ,  G06F1/32 ,  G06F13/40 ,  H04R1/10 ,  G06F7/00

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3293 ,  G06F13/102 ,  G06F13/4072 ,  G10L19/04 ,  H04R1/1091 ,  H04R2201/109 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D50/20

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

公开(公告)号：US20150228290A1

公开(公告)日：2015-08-13

申请号：US14691009

申请日：2015-04-20

Applicant: Intel Corporation

Inventor： James P. Kardach ,  Brian V. Belmont ,  Muthu K. Kumar ,  Riley W. Jackson ,  Gunner D. Danneels ,  Richard A. Forand ,  Vivek Gupta ,  Jeffrey L. Huckins ,  Kristoffer D. Fleming ,  Uma M. Gadamsetty

IPC: G10L19/04 ,  H04R1/10

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3293 ,  G06F13/102 ,  G06F13/4072 ,  G10L19/04 ,  H04R1/1091 ,  H04R2201/109 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D50/20

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract translation: 描述了一种计算系统，其包括在所述计算系统在基于非主CPU / OS的非操作状态下操作时保持活动的主系统总线。 计算系统还包括在计算系统处于基于非主CPU / OS的非操作状态之内的情况下操作功能任务的控制器。 计算系统还包括耦合到主系统总线的I / O单元，其在计算系统在基于非主CPU / OS的非主操作状态下运行时保持活动。