公开(公告)号：US10853277B2

公开(公告)日：2020-12-01

申请号：US15573114

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Cunming Liang ,  Danny Y. Zhou ,  David E. Cohen ,  James R. Harris

IPC: G06F13/16 ,  G06F3/00 ,  G06F9/50 ,  G06F13/28 ,  G06F13/42 ,  G06F9/455

Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include logic to identify a Process Address Space Identifier (PASID) for a process or container of the host device and logic to associate the PASID with an individual queue pair of a hardware device of the host device, wherein the queue pair includes two complementary queues and wherein the queue pair is owned by the process or container upon association with the PASID. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US10656873B2

公开(公告)日：2020-05-19

申请号：US15387097

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： John W. Carroll ,  David Cohen ,  James R. Harris ,  Eric Dahlen

IPC: G06F3/06

Abstract: Technologies for prioritized execution of storage commands by a data storage device include determining a priority of storage commands issued by a host and adding the storage commands to a queue of the data storage device based on the determined priority of the storage command. For example, the storage command issued by the host may be divided into sub-commands and added to a storage sub-command queue of the data storage device based on the determined priority of the storage command. The priority of the storage commands may be determined based on any suitable criteria including, for example, the host storage command queue storing the storage command, metadata associated with the storage command, the type or size of the storage command, and/or other aspects of the storage command, the host, and/or the data storage device.

公开(公告)号：US12118240B2

公开(公告)日：2024-10-15

申请号：US16987748

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Benjamin Walker ,  Sanjeev Trika ,  Kapil Karkra ,  James R. Harris ,  Steven C. Miller ,  Bishwajit Dutta

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0689

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.

公开(公告)号：US11734204B2

公开(公告)日：2023-08-22

申请号：US16825538

申请日：2020-03-20

Applicant: Intel Corporation

Inventor： Gang Cao ,  James R. Harris ,  Ziye Yang ,  Vishal Verma ,  Changpeng Liu ,  Chong Han ,  Benjamin Walker

IPC: G06F13/16 ,  G06F9/50

CPC classification number: G06F13/1668 ,  G06F9/5027

Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.

公开(公告)号：US12153962B2

公开(公告)日：2024-11-26

申请号：US16849915

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Ziye Yang ,  James R. Harris ,  Kiran Patil ,  Benjamin Walker ,  Sudheer Mogilappagari ,  Yadong Li ,  Mark Wunderlich ,  Anil Vasudevan

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/54 ,  G06F13/22 ,  H04L67/1097 ,  H04L69/16

Abstract: The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.