公开(公告)号：US10007321B2

公开(公告)日：2018-06-26

申请号：US15426876

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Eliezer Weissmann ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Jay D. Schwartz ,  Sharad C. Tripathi

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

公开(公告)号：US09594560B2

公开(公告)日：2017-03-14

申请号：US14039151

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Jay D. Schwartz

IPC: G06F1/00 ,  G06F9/30 ,  G06F11/34 ,  G06F12/08 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F9/30083 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/4893 ,  G06F11/3466 ,  G06F12/084 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括第一逻辑，用于至少部分地基于所述域的活动状态驻留，停止持续时间和存储器带宽来计算处理器域的可扩展性值，并且确定用于 该域至少部分地基于域的当前操作频率和可扩展性值。 描述和要求保护其他实施例。

公开(公告)号：US09235252B2

公开(公告)日：2016-01-12

申请号：US13724798

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Jeremy J. Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个域，包括具有至少一个核的执行指令的核心域和包括至少一个图形引擎以执行图形操作的图形域，以及功率控制器来控制处理器的功耗。 功率控制器可以包括用于接收域的优先级域的指示并且基于功率限制，一个或多个最大域频率请求和优先级域指示来动态地向域分配功率的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US09189046B2

公开(公告)日：2015-11-17

申请号：US13783978

申请日：2013-03-04

Applicant: Intel Corporation

Inventor： Xiuting C. Man ,  Michael N. Derr ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Shaun M. Conrad ,  Avinash N. Ananthakrishnan

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/32 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.