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Patent Agency Ranking
公开(公告)号：US20200004633A1
公开(公告)日：2020-01-02
申请号：US16292085
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US20230088947A1
公开(公告)日：2023-03-23
申请号：US17993591
申请日：2022-11-23
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US20210318932A1
公开(公告)日：2021-10-14
申请号：US17356157
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US12189479B2
公开(公告)日：2025-01-07
申请号：US17993591
申请日：2022-11-23
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US11048587B2
公开(公告)日：2021-06-29
申请号：US16292085
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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