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1.发明申请公开(公告)号：US20190386665A1
公开(公告)日：2019-12-19
申请号：US16455247
申请日：2019-06-27
Applicant: Intel Corporation
Inventor： Oren Shalita , Roy Sofer , Alon Cohen , Sharon Heruti , Natarajan Karthik , Kailash Chandrashekar
Abstract: An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.
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Patent Agency Ranking
公开(公告)号：US10911274B2
公开(公告)日：2021-02-02
申请号：US16586418
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Kailash Chandrashekar , Ashoke Ravi
IPC: H04L27/00 , H04L27/10 , H04L27/152 , H03M1/82 , H03M1/68
Abstract: Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.
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公开(公告)号：US20200028722A1
公开(公告)日：2020-01-23
申请号：US16586418
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Kailash Chandrashekar , Ashoke Ravi
IPC: H04L27/10 , H04L27/152 , H03M1/68 , H03M1/82
Abstract: Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.
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公开(公告)号：US20150381337A1
公开(公告)日：2015-12-31
申请号：US14318799
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Paolo Madoglio , Georgios Palaskas , Stefano Pellerano , Ashoke Ravi , Kailash Chandrashekar
CPC classification number: H04L7/0004 , G04F10/005 , H04B17/14 , H04B17/21 , H04L7/0087
Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.
Abstract translation: 该应用程序除其他外还讨论了用于改善数字 - 时间转换器（DTC）的非线性的校准系统。 在一个示例中，校准系统可以包括被配置为表示DTC的段的校准路径，配置成接收校准路径的输出和经处理的频率信息的时间到数字电路，并且提供定时误差信息 并且校准引擎被配置为从主控制器接收控制器调制信息，以向DTC提供校准调制信息以接收定时误差信息，并且使用定时误差向耦合到DTC的校正电路提供补偿信息 信息。
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5.发明授权公开(公告)号：US11171655B2
公开(公告)日：2021-11-09
申请号：US16455247
申请日：2019-06-27
Applicant: Intel Corporation
Inventor： Oren Shalita , Roy Sofer , Alon Cohen , Sharon Heruti , Natarajan Karthik , Kailash Chandrashekar
Abstract: An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.
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公开(公告)号：US09209958B1
公开(公告)日：2015-12-08
申请号：US14318799
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Georgios Palaskas , Paolo Madoglio , Stefano Pellerano , Ashoke Ravi , Kailash Chandrashekar
CPC classification number: H04L7/0004 , G04F10/005 , H04B17/14 , H04B17/21 , H04L7/0087
Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.
Abstract translation: 该应用程序除其他外还讨论了用于改善数字 - 时间转换器（DTC）的非线性的校准系统。 在一个示例中，校准系统可以包括被配置为表示DTC的段的校准路径，配置成接收校准路径的输出和经处理的频率信息的时间到数字电路，并且提供定时误差信息 并且校准引擎被配置为从主控制器接收控制器调制信息，以向DTC提供校准调制信息以接收定时误差信息，并且使用定时误差向耦合到DTC的校正电路提供补偿信息 信息。
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