公开(公告)号：US20230334613A1

公开(公告)日：2023-10-19

申请号：US18340139

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Kenneth Daxer ,  Stephen H. Gunther ,  Michael N. Derr ,  Eric Samson

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: Described herein, in one embodiment, is a graphics processor comprising a plurality of dies integrated in a package, at least one die of the plurality of dies functionally heterogeneous relative to at least one other die of the plurality of dies and manufactured with a different process technology than the at least one other die.

公开(公告)号：US20230298125A1

公开(公告)日：2023-09-21

申请号：US17827444

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  David Cowperthwaite ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Aravindh Anantaraman ,  Michael Apodaca ,  Kenneth Daxer

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T1/60 ,  G06F9/4881 ,  G06F9/5061 ,  G06F9/505 ,  G06T2200/16

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

公开(公告)号：US20230297440A1

公开(公告)日：2023-09-21

申请号：US17827373

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/5077 ,  G06F9/5016 ,  G06T1/20

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

公开(公告)号：US20230297421A1

公开(公告)日：2023-09-21

申请号：US17827346

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Hema Chand Nalluri ,  Jeffery S. Boles ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Michael Apodaca

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06T1/60 ,  G06T1/20 ,  G06F9/5038 ,  G06F9/5055

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

公开(公告)号：US20230297159A1

公开(公告)日：2023-09-21

申请号：US18185008

申请日：2023-03-16

Applicant: Intel Corporation

Inventor： Kenneth Daxer ,  Stephen H. Gunther ,  Michael N. Derr ,  Eric Samson

IPC: G06F1/3287 ,  G06F1/329

CPC classification number: G06F1/3287 ,  G06F1/329

Abstract: Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.