公开(公告)号：US20230095914A1

公开(公告)日：2023-03-30

申请号：US17485211

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gerald PASDAST ,  Sathya Narasimman TIAGARAJ ,  Adel A. ELSHERBINI ,  Tanay KARNIK ,  Robert MUNOZ ,  Kevin SAFFORD

IPC: G01R31/317 ,  G01R31/28

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.