公开(公告)号：US12113500B2

公开(公告)日：2024-10-08

申请号：US17131809

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  L Mark Elzinga ,  Martin Clara ,  Giacomo Cascio

IPC: H03H11/24 ,  H04B1/16 ,  H04W88/08

CPC classification number: H03H11/24 ,  H04B1/1607 ,  H04W88/08

Abstract: An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.