公开(公告)号：US20210240475A1

公开(公告)日：2021-08-05

申请号：US17124813

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  MARK CHARNEY ,  MICHAEL MISHAELI ,  ROBERT VALENTINE ,  ITAI RAVID ,  JASON W. BRANDT ,  GILBERT NEIGER ,  BARUCH CHAIKIN ,  EFRAIM ROTEM

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20230076318A1

公开(公告)日：2023-03-09

申请号：US17903307

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  MARK CHARNEY ,  MICHAEL MISHAELI ,  ROBERT VALENTINE ,  ITAI RAVID ,  JASON W. BRANDT ,  GILBERT NEIGER ,  BARUCH CHAIKIN ,  EFRAIM ROTEM

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20150379668A1

公开(公告)日：2015-12-31

申请号：US14319099

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  ARIK GIHON ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  ERIC C. SAMSON ,  MICHAEL MISHAELI ,  YONI AIZIK ,  CHEN RANEL

IPC: G06T1/20 ,  G09G5/18

CPC classification number: G06F9/5044 ,  G06F3/14 ,  G06F9/5083 ,  G09G2360/08

Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.

Abstract translation: 一种用于确定线程执行并行性的装置和方法。 例如，根据一个实施例的处理器包括：多个核，用于执行多个线程; 多个计数器，用于收集与所述多个核上的所述多个线程的执行相关的数据; 依赖关系分析模块，用于分析与线程的执行有关的数据，并且响应地确定线程间相关性的级别; 以及控制模块，用于基于确定的线程间依赖性水平来响应地调整多个核心的操作。