公开(公告)号：US20250061203A1

公开(公告)日：2025-02-20

申请号：US18724426

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Shamanna DATTA ,  Mahesh NATU ,  Jiewen YAO ,  Xiaoyu RUAN ,  Andrew Martyn DRAPER ,  Raghunandan MAKARAM ,  Alberto MUNOZ

IPC: G06F21/57 ,  G06F21/53 ,  G06F21/54

Abstract: A method comprises establishing, in a trusted security manager of a trusted execution environment, a device update pre-authentication policy for a device communicatively coupled to the trusted execution manager, providing the device update pre-authentication policy to the device, receiving, from the device, a pre-authentication event signal, and providing, to the device, a pre-authentication event response comprising an update indicator to indicate to the device whether a runtime update may be performed.

公开(公告)号：US20220179961A1

公开(公告)日：2022-06-09

申请号：US17576650

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Jiewen YAO ,  David HARRIMAN ,  Xiaoyu RUAN ,  Mahesh NATU

IPC: G06F21/57 ,  G06F13/42 ,  G06F13/40 ,  G06F21/85

Abstract: Various embodiments provide apparatuses, systems, and methods for establishing, by a data object exchange (DOE entity) of a peripheral component interconnect express (PCIe) device, a first session for communication between a first host entity of a host device and a first PCIe entity of the PCIe device, and a second session for communication between a second host entity of the host device and a second PCIe entity of the PCIe device. The first session may have a first security policy and be a session of a first connection between the PCIe device and the host device. The second session may have a second security policy and be a session of a second connection between the PCIe device and the host device. Other embodiments may be described and claimed.

公开(公告)号：US20210271539A1

公开(公告)日：2021-09-02

申请号：US17171790

申请日：2021-02-09

Applicant: Intel Corporation

Inventor： Balaji VEMBU ,  Bryan WHITE ,  Ankur SHAH ,  Murali RAMADOSS ,  David PUFFER ,  Altug KOKER ,  Aditya NAVALE ,  Mahesh NATU

IPC: G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20220398147A1

公开(公告)日：2022-12-15

申请号：US17849356

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Balaji VEMBU ,  Bryan WHITE ,  Ankur SHAH ,  Murali RAMADOSS ,  David PUFFER ,  Altug KOKER ,  Aditya NAVALE ,  Mahesh NATU

IPC: G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20190138756A1

公开(公告)日：2019-05-09

申请号：US15980455

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Mahesh NATU ,  Eric DAHLEN

IPC: G06F21/85 ,  H04L29/06 ,  G06F13/40

CPC classification number: G06F21/85 ,  G06F13/4027 ,  G06F2221/2141 ,  H04L63/101 ,  H04L63/104 ,  H04L63/20

Abstract: A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.