公开(公告)号：US12068314B2

公开(公告)日：2024-08-20

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  William Hsu ,  Biswajeet Guha ,  Martin Weiss ,  Apratim Dhar ,  William T. Blanton ,  John H. Irby, IV ,  James F. Bondi ,  Michael K. Harper ,  Charles H. Wallace ,  Tahir Ghani ,  Benedict A. Samuel ,  Stefan Dickert

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US10720345B1

公开(公告)日：2020-07-21

申请号：US16125248

申请日：2018-09-07

Applicant: Intel Corporation

Inventor： Mauro J. Kobrinsky ,  Myra McDonnell ,  Brennen K. Mueller ,  Chytra Pawashe ,  Daniel Pantuso ,  Paul B. Fischer ,  Lance C. Hibbeler ,  Martin Weiss

IPC: H01L21/30 ,  H01L21/67

Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.

公开(公告)号：US11748869B1

公开(公告)日：2023-09-05

申请号：US16504695

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Martin Weiss ,  Apratim Dhar ,  Aaron M. White

IPC: G06T7/00 ,  G06T7/73 ,  G06V10/75 ,  H01L23/498 ,  H01L23/544 ,  G03F1/44 ,  G03F1/42

CPC classification number: G06T7/001 ,  G03F1/42 ,  G03F1/44 ,  G06T7/74 ,  G06V10/751 ,  H01L23/49838 ,  H01L23/544 ,  G06T2207/30148 ,  H01L2223/54426

Abstract: Embodiments disclosed herein include a lithography reticle set and methods of using such reticle sets. In an embodiment, the set comprises a first reticle and a second reticle. In an embodiment, the first reticle comprises a first grating having a first pitch, and a second grating having a second pitch. In an embodiment, the second reticle comprises a third grating having a third pitch, wherein the third pitch is different than the first pitch, and a fourth grating having a fourth pitch, wherein the fourth pitch is different than the first pitch. In an embodiment the third grating overlaps the first grating and the fourth grating overlaps the second grating when two or more edges of the first reticle are aligned with two or more edges of the second reticle. In an embodiment the first reticle or the second reticle further comprises a pattern recognition feature.