公开(公告)号：US12008067B2

公开(公告)日：2024-06-11

申请号：US17527324

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Mathew Nevin ,  Jorge Parra ,  Ashutosh Garg ,  Shubra Marwaha ,  Shubh Shah

IPC: G06F17/16 ,  G06F7/487 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F17/16 ,  G06F7/4876 ,  G06F9/3001 ,  G06F9/30036 ,  G06F13/1673 ,  G06F2207/3892

Abstract: An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration hardware to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce multiply-add operations to be performed by the matrix multiplication hardware.

公开(公告)号：US11188618B2

公开(公告)日：2021-11-30

申请号：US16561715

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Mathew Nevin ,  Jorge Parra ,  Ashutosh Garg ,  Shubra Marwaha ,  Shubh Shah

IPC: G06F17/16 ,  G06F7/487 ,  G06F9/30 ,  G06F13/16

Abstract: An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration hardware to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce multiply-add operations to be performed by the matrix multiplication hardware.