公开(公告)号：US20240332088A1

公开(公告)日：2024-10-03

申请号：US18129617

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Swapnadip Ghosh ,  Chiao-Ti Huang ,  Matthew Prince ,  Jeffrey Miles Tan ,  Ramy Ghostine ,  Anupama Bowonder

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823456 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: One or more transistors may have gate structures with differing sidewall slopes. The gate structures may be over stacks of channel regions in nanosheets (or nanoribbons or nanowires), and the differing gate profiles may correspond to differing electrical characteristics. Transistors with metal gate structures may be tuned by strategically etching the gate structures, for example, using lower etch powers, higher etch temperatures, and/or longer etch durations, to achieve substantially vertical gate profiles.

公开(公告)号：US20240332290A1

公开(公告)日：2024-10-03

申请号：US18129700

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Patrick Morrow ,  Nikhil Mehta ,  Leonard Guler ,  Sudipto Naskar ,  Alison Davis ,  Dan Lavric ,  Matthew Prince ,  Jeanne Luce ,  Charles Wallace ,  Cortnie Vogelsberg ,  Rajaram Pai ,  Caitlin Kilroy ,  Jojo Amonoo ,  Sean Pursel ,  Yulia Gotlib

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

公开(公告)号：US20250006810A1

公开(公告)日：2025-01-02

申请号：US18216514

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Manish Chandhok ,  Marvin Paik ,  Shahidul Haque ,  Jason Klaus ,  Asad Iqbal ,  Patrick Morrow ,  Nikhil Mehta ,  Alison Davis ,  Sean Pursel ,  Steven Shen ,  Christopher Rochester ,  Matthew Prince

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

Abstract: Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. The underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.