公开(公告)号：US10599178B2

公开(公告)日：2020-03-24

申请号：US16036419

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

IPC: G06F1/12 ,  G06F13/42

Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

公开(公告)号：US10353146B2

公开(公告)日：2019-07-16

申请号：US15635881

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Michael C. Rifani ,  Sasha N. Oster ,  Adel A. Elsherbini

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/42 ,  H05K1/02 ,  H04B10/80

Abstract: Various embodiments disclosed relate to a stretchable packaging system. The system includes a first electronic component. The first electronic component includes a first optical emitter. The system further includes a second electronic component. The second electronic component includes a first receiver. An optical interconnect including a first elastomer having a first refractive index connects the first optical emitter to the first receiver. An encapsulate layer including a second elastomer having a second refractive index at least partially encapsulates the first electronic component, the second electronic component, and the optical interconnect.

公开(公告)号：US20190056761A1

公开(公告)日：2019-02-21

申请号：US16036419

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

IPC: G06F1/12 ,  G06F13/42

CPC classification number: G06F1/12 ,  G06F13/4291

Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.