公开(公告)号：US20220171648A1

公开(公告)日：2022-06-02

申请号：US17440701

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Bryan J. Rodriguez ,  Kshitij A. Doshi ,  Ned M. Smith ,  Michael G. Millsap

IPC: G06F9/455 ,  G06F9/50

Abstract: In one embodiment, a computing device comprises memory circuitry and processing circuitry. The memory circuitry is to store a plurality of container images, comprising: a first container image comprising a first set of applications; and a second container image comprising a virtual machine, a guest operating system, and a second set of applications. The processing circuitry is to: instantiate a plurality of containers on a host operating system, wherein the plurality of containers comprises a first container and a second container; execute the first set of applications in the first container, wherein the first set of applications is to be executed on the host operating system; and execute the virtual machine in the second container, wherein the guest operating system is to be executed on the virtual machine and the second set of applications is to be executed on the guest operating system.

公开(公告)号：US12032977B2

公开(公告)日：2024-07-09

申请号：US17440701

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Bryan J. Rodriguez ,  Kshitij A. Doshi ,  Ned M. Smith ,  Michael G. Millsap

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/455 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/5077 ,  G06F2009/45562 ,  G06F2009/45583

Abstract: In one embodiment, a computing device comprises memory circuitry and processing circuitry. The memory circuitry is to store a plurality of container images, comprising: a first container image comprising a first set of applications; and a second container image comprising a virtual machine, a guest operating system, and a second set of applications. The processing circuitry is to: instantiate a plurality of containers on a host operating system, wherein the plurality of containers comprises a first container and a second container; execute the first set of applications in the first container, wherein the first set of applications is to be executed on the host operating system; and execute the virtual machine in the second container, wherein the guest operating system is to be executed on the virtual machine and the second set of applications is to be executed on the guest operating system.

公开(公告)号：US20200250003A1

公开(公告)日：2020-08-06

申请号：US16652038

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Yen-Kuang Chen ,  Ragaad Mohammed Irsehid Altarawneh ,  Juan Pablo Munoz Chiabrando ,  Siew Wen Chin ,  Kushal Datta ,  Subramanya R. Dulloor ,  Julio C. Zamora Esquivel ,  Omar Ulises Florez Choque ,  Vishakha Gupta ,  Scott D. Hahn ,  Rameshkumar Illikkal ,  Nilesh Kumar Jain ,  Siti Khairuni Amalina Kamarol ,  Anil S. Keshavamurthy ,  Heng Kar Lau ,  Jonathan A. Lefman ,  Yiting Liao ,  Michael G. Millsap ,  Ibrahima J. Ndiour ,  Luis Carlos Maria Remis ,  Addicam V. Sanjay ,  Usman Sarwar ,  Eve M. Schooler ,  Ned M. Smith ,  Vallabhajosyula S. Somayazulu ,  Christina R. Strong ,  Omesh Tickoo ,  Srenivas Varadarajan ,  Jesús A. Cruz Vargas ,  Hassnaa Moustafa ,  Arun Raghunath ,  Katalin Klara Bartfai-Walcott ,  Maruti Gupta Hyde ,  Deepak S. Vembar ,  Jessica McCarthy

IPC: G06F9/50 ,  G06K9/00 ,  G06N3/04 ,  G06N3/063

Abstract: In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.