公开(公告)号：US20190206753A1

公开(公告)日：2019-07-04

申请号：US15859483

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Mohit MAMODIA ,  Paul START ,  Ken HACKENBERG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L23/29 ,  H01L25/07

CPC classification number: H01L23/3114 ,  H01L23/291 ,  H01L23/49506 ,  H01L23/562 ,  H01L25/074

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package including a die on a substrate, where the die has a front side surface electrically coupled to the substrate and a backside surface that is opposite from the front side surface. The semiconductor package also has a bicontinuous ceramic composite (BCC) stiffener on the backside surface of the die. The BCC stiffener may include one or more materials, including porous ceramics, polymeric resins, and metals. The BCC stiffener may be directly coupled to the backside surface of the die without an adhesive layer. The BCC stiffener may be disposed on the die to reduce warpage based on the substrate and die. The semiconductor package may have the BCC stiffener formed with the one or more materials using a polymeric resin in a liquid state process and a resin pre-loaded in a ceramic process.

公开(公告)号：US20170186707A1

公开(公告)日：2017-06-29

申请号：US14998096

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Shweta AGRAWAL ,  Hao WU ,  Mohit MAMODIA ,  Shengquan E. OU ,  Hualiang SHI

IPC: H01L23/58 ,  H01L21/78 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/585 ,  H01L21/76885 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/5283 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.