公开(公告)号：US20200050570A1

公开(公告)日：2020-02-13

申请号：US16659660

申请日：2019-10-22

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Nitish Paliwal

IPC: G06F13/40 ,  G06F13/20

Abstract: In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.

公开(公告)号：US11816052B2

公开(公告)日：2023-11-14

申请号：US16659660

申请日：2019-10-22

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Nitish Paliwal

IPC: G06F13/40 ,  G06F13/20

CPC classification number: G06F13/4022 ,  G06F13/20

Abstract: In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.

公开(公告)号：US11366773B2

公开(公告)日：2022-06-21

申请号：US16840266

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Peeyush Purohit ,  Nitish Paliwal ,  Archana Srinivasan

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0877 ,  G06F12/0815

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

公开(公告)号：US20200328879A1

公开(公告)日：2020-10-15

申请号：US16946470

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Raghunandan Makaram ,  Ishwar Agarwal ,  Kirk S. Yap ,  Nitish Paliwal ,  David J. Harriman ,  Ioannis T. Schoinas

IPC: H04L9/06 ,  G06F21/62 ,  H04L1/18

Abstract: An apparatus includes a port with circuitry to implement one or more layers of a Compute Express Link (CXL)-based protocol. The port includes an agent to obtain information to be transmitted to another device over a link based on the CXL-based protocol via a flit, encrypt at least a portion of the information to yield a ciphertext, generate a cyclic redundancy check (CRC) code based on the ciphertext, and cause a flit to be generated comprising the ciphertext. The port is to use the circuitry to transmit the flit and the CRC code to the other device over the link.

公开(公告)号：US20220197852A1

公开(公告)日：2022-06-23

申请号：US17692031

申请日：2022-03-10

Applicant: Intel Corporation

Inventor： Mohan Nair ,  Ishwar Agarwal ,  Ashish Gupta ,  Peeyush Purohit ,  Vijay Pothi Raj Govindaraj ,  Nitish Paliwal ,  Rahul Boyapati ,  Minjer Juan

IPC: G06F15/173 ,  G06F9/50

Abstract: A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

公开(公告)号：US11201838B2

公开(公告)日：2021-12-14

申请号：US16582224

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Pratik Marolia ,  Rajesh Sankaran ,  Ishwar Agarwal ,  Nitish Paliwal

IPC: H04L12/935 ,  H04L29/06

Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.

公开(公告)号：US20200334179A1

公开(公告)日：2020-10-22

申请号：US16840266

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Peeyush Purohit ,  Nitish Paliwal ,  Archana Srinivasan

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

公开(公告)号：US20200021540A1

公开(公告)日：2020-01-16

申请号：US16582224

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Pratik Marolia ,  Rajesh Sankaran ,  Ishwar Agarwal ,  Nitish Paliwal

IPC: H04L12/935 ,  H04L29/06

Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.

公开(公告)号：US20190095363A1

公开(公告)日：2019-03-28

申请号：US16141729

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Peeyush Purohit ,  Nitish Paliwal ,  Archana Srinivasan

IPC: G06F13/16 ,  G06F13/42 ,  G06F11/10

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.